PIC18F4620-I/ML【PDF 198/286 页】IC MCU FLASH 32KX16 44QFN

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Sheet目录3818

194页 195页 196页 197页 [198页]199页 200页 201页 202页

2001 Microchip Technology Inc.

Advance Information

DS39541A-page 307

PIC18C601/801

INDEX

A/D ................................................................................... 193

A/D Converter Flag (ADIF Bit) ................................. 195

A/D Converter Interrupt, Configuring ....................... 197

ADCON0 Register .......................................... 193

, 195

ADCON1 Register .......................................... 193

, 194

ADCON2 Register ................................................... 193

ADRES Register ............................................. 193

, 195

Analog Port Pins, Configuring ................................. 199

Associated Registers ............................................... 201

Block Diagram ......................................................... 196

Block Diagram, Analog Input Model ........................ 197

Configuring the Module ........................................... 197

Conversion Clock (TAD) ........................................... 199

Conversion Status (GO/DONE Bit) .......................... 195

Conversions ............................................................. 200

Converter Characteristics ............................... 272

, 292

Effects of a RESET .................................................. 206

Equations

Acquisition Time .............................................. 198

Minimum Charging Time ................................. 198

Operation During SLEEP ......................................... 206

Sampling Requirements .......................................... 198

Sampling Time ......................................................... 198

Special Event Trigger (CCP) .......................... 144

, 200

Timing Diagram ....................................................... 293

Absolute Maximum Ratings ............................................. 265

Access Bank ...................................................................... 58

ADCON0 Register ........................................................... 193

GO/DONE Bit .......................................................... 195

Registers

ADCON2 (A/D Control 2) ................................. 195

ADCON1 Register .................................................. 193

, 194

ADCON2 Register ........................................................... 193

ADDLW ............................................................................ 221

ADDWF ............................................................................ 221

ADDWFC ......................................................................... 222

ADRES Register ..................................................... 193

, 195

AKS .................................................................................. 167

Analog-to-Digital Converter. See A/D

ANDLW ............................................................................ 222

ANDWF ............................................................................ 223

Assembler

MPASM Assembler ................................................. 259

Bank Select Register ......................................................... 58

Baud Rate Generator ....................................................... 164

Associated Registers ............................................... 179

BC .................................................................................... 223

BCF .................................................................................. 224

BF .................................................................................... 167

Block Diagram ................................................................. 119

Block Diagrams

A/D ........................................................................... 196

Baud Rate Generator .............................................. 164

Capture Mode Operation ......................................... 143

Compare Mode Operation ....................................... 144

Interrupt Logic ............................................................ 90

Low Voltage Detect ................................................. 203

MSSP

I2C Mode ......................................................... 159

SPI Mode ......................................................... 153

On-Chip Reset Circuit, Simplified .............................. 29

Phase Lock Loop ...................................................... 23

PORTA

RA3:RA0 and RA5 Pins .................................. 103

RA4/T0CKI Pin ................................................ 104

PORTB

RB3 Pin ........................................................... 106

RB3:RB0 Port Pins .......................................... 106

RB7:RB4 Port Pins .......................................... 105

PORTC .................................................................... 108

PORTD

I/O Mode ......................................................... 110

System Bus Mode ........................................... 111

PORTD (In I/O Port Mode) ...................................... 124

PORTE

I/O Mode ......................................................... 113

System Bus Mode ........................................... 114

PORTF

RF2:RF0 Pins .................................................. 116

RF5:RF3 Pins .................................................. 117

RF7:RF6 Pins .................................................. 117

PORTG

I/O Mode ......................................................... 119

System Bus Mode ........................................... 120

PORTH

RH3:RH0 Pins (I/O Mode) ............................... 121

RH3:RH0 Pins (System Bus Mode) ................ 122

RH7:RH4 Pins ................................................. 121

PORTJ

I/O Mode ......................................................... 124

System Bus Mode ........................................... 125

Simplified PWM Diagram ........................................ 146

SSP (SPI Mode) ...................................................... 153

Timer0

16-bit Mode ..................................................... 128

8-bit Mode ....................................................... 128

Timer1 ..................................................................... 131

16-bit R/W Mode ............................................. 132

Timer2 ..................................................................... 136

Timer3 ..................................................................... 138

16-bit R/W Mode ............................................. 138

USART

Asynchronous Receive ................................... 185

Asynchronous Transmit .................................. 183

Watchdog Timer ...................................................... 211

BN ................................................................................... 224

BNC ................................................................................. 225

BNN ................................................................................. 225

BNOV .............................................................................. 226

BNZ ................................................................................. 226

BOV ................................................................................. 229

BRA ................................................................................. 227

BRG ................................................................................. 164

BSF ................................................................................. 227

BSR. See Bank Select Register.

BTFSC ............................................................................. 228

BTFSS ............................................................................. 228

BTG ................................................................................. 229

Bus .................................................................................. 176

Bus Collision During a RESTART Condition ................... 175

Bus Collision During a START Condition ........................ 173

Bus Collision During a STOP Condition .......................... 176

BZ .................................................................................... 230

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